LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity console_buffer is
  port (clk : in std_logic;
		
		addr_r : in std_logic_vector(10 downto 0);
		d_r : out std_logic_vector(7 downto 0);
		
		addr_w : in std_logic_vector(10 downto 0);
		wr_en : in std_logic;
		cs : in std_logic;
		c_w : in std_logic_vector(7 downto 0));
end entity;

architecture rtl of console_buffer is
	type memory is array(integer range<>) of std_logic_vector(7 downto 0);
	signal chars : memory(1200 downto 0);
begin
	process(addr_r, clk)
	begin
		if (rising_edge(clk)) then
			d_r <= chars(to_integer(unsigned(addr_r)));
		end if;
	end process;
	
	process(clk, addr_w, c_w, wr_en)
	begin
		if (rising_edge(clk)) then
			if (unsigned(addr_w) < 1200) and (wr_en = '1') and (cs = '1') then
				chars(to_integer(unsigned(addr_w))) <= c_w;
			end if;
		end if;
	end process;
end rtl;
